It is well known that semiconductor wafer substrates (or wafers) go through a series of semiconductor processing steps such as deposition, photolithography, etching, doping, polishing, packaging, and others, to fabricate integrated circuit (IC) chips. For example, one such commercially available wafer photoresist stabilization process may be used to enhance the adhesion of photoresist materials to the wafer substrates and reduce or eliminate critical defects caused by photoresist mask deformation after features are defined by lithography. Another example of a commercially available wafer charge clear process may be used to remove charge that may be generated during device manufacturing or presence of high electric fields caused by implantation, annealing, chemical vapor deposition (CVD), thermal cycling and other high-energy processes. Yet another example of commercially available wafer memory erasure process may be used to fully erase and deprogram for erasable programmable read-only memory (EPROM) device wafer.
During the wafer photoresist stabilization or charge clear or memory erasure process, it is common for a wafer chuck, which is used to mount the wafer, to undergo numerous heating and cooling cycles. These cycles typically induce thermal stress in the wafer chuck, which results in the generation of minor cracks. The presence of minor cracks causes leaks in coolant that may be used to cool the wafer chuck. Traditional techniques for detecting leakage are often not responsive enough to avoid wastage of material in the form of scrapped wafers.
From the foregoing discussion, it is desirable to provide tools and techniques to improve early detection, performance, reliability and lower cost of detecting leaks during the wafer hardening process.